The use of cyclic codes to add redundancy for error detection and correction is a well known and much used technique in digital processing. One of the reasons for the favor of the cyclic redundancy check is that the encoding and decoding process is efficient because little, if any, storage is required. This is because the code words are generated by shifting and exclusive ORing ("XORing").
Nonetheless, the speed of computation of prior art techniques for cyclic encoding in digital processors is limited by the need for three processor operations for each bit processed, that is, a shift, an XOR and a compare. As digital data transmission rates increase, with improvements in technology, cyclic encoding in real time is becoming a problem. Without real time cyclic encoding, such encoding must be deferred, requiring, potentially, large amounts of memory. Furthermore, in some applications real time encoding may be a necessity.
Thus, there is a need for an approach to cyclic encoding that improves the speed of such computations. The present invention provides such an approach.